In the production of integrated circuits, it is generally attempted to integrate the components used to construct these circuits in a manner that saves as much space as possible. In circuits such as memory chips, for instance, where there is a particularly great need to achieve an integration density that is as high as possible, the structural dimensions of the components are often at the resolution limit of the lithographic projection system used to form the structures.
On the other hand, the formation of the smallest possible areas for the doped regions of the components is often at odds with the condition of a minimum size for the contact area for connection to interconnects for connecting to other components. This is justified primarily with the disadvantageously increasing contact resistances toward smaller contact areas.
Therefore, the aim is to align a contact plug (just called contact hereinafter) with its contact area as precisely as possible with the area of the doped region. In the case of present-day technology generations, the alignment tolerance (overlay) is typically 0.35 F, where F is the minimum structural dimension that can be produced.
The self-aligned contact-making methods (self-aligned contact, SAC) have proved to be advantageous for forming a large, effective contact area between the doped regions and the contacts. In the case of such a method, lateral spacers and an insulation cap which encapsulate a word line or gate, for example, are used to etch out a space that lies between two spacers and is filled with an insulator in a highly selective etching process without the alignment error of the resist mask used for the contact opening having an effect. The position of the contact is defined solely by the word lines and their spacers.
The contacts are thereby applied exactly to the contact doping regions. The latter have previously been implanted in a self-aligned manner in addition to the word lines and spacers. A higher packing density of the contacts and an improved reproducibility are thereby achieved.
Previous self-aligned methods for forming contacts are also associated with disadvantages, however. By way of example, contacts which are formed by means of salicide technology and in which sputtered-on metal layers are subjected to a siliconization process are subject to restrictions in the selection of the material and lead to consequential damage in the components at high temperatures in the subsequent processes. Moreover, in this technology, problems arise with regard to the linking of the contacts to difficult surface topographies, such as in the case of so-called strap contacts, for instance.
Self-aligned contacts with the aid of hole-type contact masks at word lines situated in an insulating manner are associated with the disadvantage that, on account of the above-specified tolerance of 0.35 F for the required positional accuracy by means of a mask process, a minimum width of 1.7 F is required for the word line ridge provided with doped regions from both sides.
Furthermore, there is the problem in this case that, with progressive reduction of the structural dimensions in the components, the aspect ratios of the trenches, i.e. the ratio of depth to width of the trench between the word lines or gates of field-effect transistors, become larger and larger. In this case, so-called voids arise to an increased extent in the course of filling with an insulator. As a result, short circuits between adjacent contacts may arise during the filling of the contact holes with conductive contact material.
So-called “Line type Self-Aligned Contacts” are known as a solution. In this case, transversely with respect to the word lines, an elongate hole is opened in the insulator deposited on the word lines. The corresponding etching process stops with high selectivity on the contact doping regions and on the spacers encapsulating the word line and on the insulation covering cap. Afterward, conductive contact material is deposited and planarized back to an extent such that, when the insulation cap of the word lines is uncovered, the filled contact material is separated into two partial regions on the two sides of the ridge. The problem of voids arising in closely adjacent contact openings is in this case reduced by the subsequent introduction of a spacer into the contact opening. A corresponding method is described in K. H. Yoon et al., 2001 Symposium on VLSI Technology, 10-4.
A further proposal, described in T. Yoon et al., 1999 Symposium on VLSI Technology 37–39, is based on firstly forming contact plugs and only then filling the spaces that remain between them with insulator material. In this case, voids that possibly arise do not pose a problem since the contacts have already been formed.
This method called pre-poly-plug technique (P3) is also associated with disadvantages:                1. According to this technique, it is necessary to create the contacts for connection to the doped regions of the components in a common process step. Consequently, it is not possible to simultaneously adapt the contact material to all doping types (n-type doping or p-type doping) and dopant concentrations (for instance n-type doping or n+-type doping) present in the integrated circuit.        2. The contacts produced at the outset are exposed to a number of subsequent thermal processes due to their early production. As a result, a considerable degradation of the component may occur at the contact area, as a result of which the relevant component may be damaged.        3. The formation of the contacts in accordance with the P3 technique may necessitate an increased number of contact interfaces since contacts have to be stacked one above the other. However, contact interfaces represent a source for an increase in the resistance and for the reduction of the reliability of the contacts.        